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description available in so-8 package, the hcpl-0708 optocoupler utilizes the latest cmos ic technology to achieve out - standing performance with very low power consump - tion. basic building blocks of the hcpl-0708 are a high speed led and a cmos detector ic. the detector incor - porates an integrated photodiode, a high-speed trans- impedance amplifer, and a voltage comparator with an output driver. features ? +5 v cmos compatibility ? 15 ns typical pulse width distortion ? 30 ns max. pulse width distortion ? 40 ns max. propagation delay skew ? high speed: 15 mbd ? 60 ns max. propagation delay ? 10 kv/s minimum common mode rejection ? C40 to 100c temperature range ? safety and regulatory approvals pending C ul recognized 3750 v rms for 1 min. per ul 1577 for hcpl-0708 C csa component acceptance notice #5 C iec/en/din en 60747-5-2 approved for hcpl-0708 option 060 applications ? scan drive in pdp ? digital feld bus isolation: devicenet, sds, profbus ? multiplexed data transmission ? computer peripheral interface ? microprocessor system interface functional diagram *a 0.1 f bypass capacitor must be connected between pins 5 and 8. hcpl-0710 functional diagram 8 7 6 1 3 5 2 4 nc anode cathode nc v dd v o gnd led off on truth table nc v o , output h l hcpl-0708 high speed cmos optocoupler data sheet lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-free product caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd.
ordering information hcpl-0708 is ul recognized with 3750 vrms for 1 minute per ul1577. option part rohs non rohs surface gull tape ul 5000 vrms/ iec/en/din number compliant compliant package mount wing & reel 1 minute rating en 60747-5-2 quantity -000e no option so-8 x 100 per tube hcpl-0708 -500e #500 x x 1500 per reel -560e - x x x 1500 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example1: hcpl-0708-500e to order product of small outline so-8 package in tape and reel packaging and rohs compliant. example 2: hcpl-0708 to order product of small outline so-8 package in tube packaging and non rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. remarks: the notation #xxx is used for existing products, while (new) products launched since july 15, 2001 and rohs compliant will use Cxxxe.
package outline drawing xxxv yw w 8 7 6 5 4 3 2 1 5.994 0.203 (0.236 0.008) 3.937 0.127 (0.155 0.005) 0.406 0.076 (0.016 0.003) 1.270 (0.050) bsc 5.080 0.127 (0.200 0.005) 3.175 0.127 (0.125 0.005) 1.524 (0.060) 45 x 0.432 (0.017) 0.228 0.025 (0.009 0.001) type number (last 3 digits) date code 0.305 (0.012) min. total package length (inclusive of mold flash) 5.207 0.254 (0.205 0.010) dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches) max. option number 500 not marked . note: floating lead protrusion is 0.15 mm (6 mils) max. 0.203 0.102 (0.008 0.004) 7 pin one 0 ~ 7 * * 7.49 (0.295) 1.9 (0.075) 0.64 (0.025) land pattern recommendation
solder refow thermal profle regulatory information the hcpl-0708 has been approved by the following organizations: ul recognized under ul 1577, component recognition program, file e55361. csa approved under csa component acceptance notice #5, file ca88324. iec/en/din en 60747-5-2 approved under: iec 60747-5-2:1997 + a1:2002 en 60747-5-2:2001 + a1:2002 din en 60747-5-2 (vde 0884teil 2):2003-01 (option 060 only) 0 time (seconds) temperature (c) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec. 160c 140c 150c peak temp . 245c peak temp . 240c peak temp. 230c soldering tim e 200c preheating tim e 150c, 90 + 30 sec. 2.5c 0.5c/sec. 3c + 1c/?0.5c tight typical loos e room temperature preheating rate 3c + 1c/?0.5c/sec. reflow heating rate 2.5c 0.5c/sec. recommended pb-free ir profle 217 c ramp-d ow n 6 c/sec. max. ramp-u p 3 c/sec . max . 150 - 200 c 260 +0/-5 c t 25 c to pea k 60 to 150 sec. 20-40 sec. time w ithin 5 c of ac tu al peak tempera t ure t p t s prehea t 60 to 180 sec. t l t l t smax t smin 25 t p tim e tempera ture no tes: the time fr om 25 c to peak tempera ture = 8 minutes max. t smax = 200 c, t smin = 150 c note: non-halide fux should be used. note: non-halide fux should be used.
insulation and safety related specifcations parameter symbol value units conditions minimum external air l(i01) 4.9 mm measured from input terminals to output gap (clearance) terminals, shortest distance through air. minimum external l(i02) 4.8 mm measured from input terminals to output tracking (creepage) terminals, shortest distance path along body. minimum internal plastic 0.08 mm insulation thickness between emitter and gap (internal clearance) detector; also known as distance through insulation. tracking resistance cti 175 volts din iec 112/vde 0303 part 1 (comparative tracking index) isolation group iiia material group (din vde 0110, 1/89, table 1) all avago data sheets report the creepage and clearance inherent to the optocoupler component itself. these dimen sions are needed as a starting point for the equip - ment designer when determining the circuit insulation requirements. however, once mounted on a printed circuit board, minimum creepage and clearance require - ments must be met as specifed for individual equipment standards. for creepage, the shortest distance path along the surface of a printed circuit board between the solder fllets of the input and output leads must be considered. there are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. creepage and clearance distances will also change depending on fac - tors such as pollution degree and insulation level.
iec/en/din en 60747-5-2 insulation related characteristics (option 060) description symbol hcpl-0708 option 060 units installation classifcation per din vde 0110/1.89, table 1 for rated mains voltage 150 v rms i-iv for rated mains voltage 300 v rms i-iii for rated mains voltage 450 v rms climatic classifcation 55/85/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage v iorm 560 v peak input to output test voltage, method b? v pr 1050 v peak v iorm x 1.875 = v pr , 100% production test with t m = 1 sec, partial discharge < 5 pc input to output test voltage, method a? v pr 840 v peak v iorm x 1.5 = v pr , type and sample test, t m = 60 sec, partial discharge < 5 pc highest allowable overvoltage? v iotm 4000 v peak (transient overvoltage, t ini = 10 sec) safety limiting values (maximum values allowed in the event of a failure, also see thermal derating curve, figure 11.) case temperature t s 150 c input current i s,input 150 ma output power p s,output 600 mw insulation resistance at t s , v 10 = 500 v r io 10 9 ? ?refer to the front of the optocoupler section of the isolation and control component designers catalog, under product safety regulations sec - tion iec/en/din en 60747-5-2, for a detailed description. recommended operating conditions parameter symbol min. max. units figure ambient operating temperature t a C40 +100 c supply voltages v dd 4.5 5.5 v input current (on) i f 10 16 ma 1, 2 absolute maximum ratings parameter symbol min. max. units figure storage temperature t s C55 125 c ambient operating temperature [1] t a C40 +100 c supply voltages v dd 0 6 volts output voltage v o C0.5 v dd2 +0.5 volts average output current i o 2 ma average forward input current i f 20 ma lead solder temperature 260c for 10 sec., 1.6 mm below seating plane solder refow temperature profle see solder refow temperature profle section
electrical specifcations over recommended temperature (t a = C40c to +100c) and 4.5 v v dd 5.5 v. all typical specifcations are at t a = 25c, v dd = +5 v. parameter symbol min. typ. max. units test conditions fig. notes input forward voltage v f 1.3 1.5 1.8 v i f = 12 ma 1 input reverse bv r 5 v i r = 10 a breakdown voltage logic high output v oh 4.0 4.8 v i f = 0, i o = C20 a voltage logic low output v ol 0.01 0.1 v i f = 12 ma, i o = 20 a voltage input threshold current i th 8.2 ma i ol = 20 a 2 logic low output i ddl 6.0 14.0 ma i f = 12 ma 4 supply current logic high output i ddh 4.5 11.0 ma i f = 0 3 supply current switching specifcations over recommended temperature (t a = C40c to +100c) and 4.5 v v dd 5.5 v. all typical specifcations are at t a = 25c, v dd = +5 v. parameter symbol min. typ. max. units test conditions fig. notes propagation delay time t phl 20 35 60 ns i f = 12 ma, c l = 15 pf 5 1 to logic low output cmos signal levels propagation delay time t plh 13 21 60 ns i f = 12 ma, c l = 15 pf 5 1 to logic high output cmos signal levels pulse width pw 100 ns pulse width distortion |pwd| 0 14 30 ns i f = 12 ma, c l = 15 pf 2 2 cmos signal levels propagation delay skew t psk 40 ns i f = 12 ma, c l = 15 pf 3 3 cmos signal levels output rise time t r 20 ns i f = 12 ma, c l = 15 pf (10 - 90%) cmos signal levels output fall time t f 25 ns i f = 12 ma, c l = 15 pf (90 - 10%) cmos signal levels common mode |cm h | 10 15 kv/s v cm = 1000 v, t a = 25c, 4 4 transient immunity at i f = 0 ma logic high output common mode |cm l | 10 15 kv/s v cm = 1000 v, t a = 25c, 5 5 transient immunity at i f = 12 ma logic low output
package characteristics all typicals at t a = 25c. parameter symbol min. typ. max. units test conditions input-output insulation i i-o 1 a 45% rh, t = 5 s v i-o = 3 kv dc, t a = 25c input-output momentary v iso 3750 vrms rh 50%, t = 1 min., withstand voltage t a = 25c input-output resistance r i-o 10 12 ? v i-o = 500 v dc input-output capacitance c i-o 0.6 pf f = 1 mhz, t a = 25c notes: 1. t phl propagation delay is measured from the 50% level on the risiing edge of the input pulse to the 2.5 v level of the falling edge of the v o signal. t plh propagation delay is measured from the 50% level on the falling edge of the input pulse to the 2.5 v level of the rising edge of the v o signal. 2. pwd is defned as |t phl - t plh |. 3. t psk is equal to the magnitude of the worst case diference in t phl and/or t plh that will be seen between units at any given temperature within the recommended operating conditions. 4. cm h is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. 5. cm l is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
figure 1. typical input diode forward characteristic. figure 2. typical input threshold current vs. temperature. figure 3. typical logic high o/p supply current vs. temperature. figure 4. typical logic low o/p supply current vs. temperature. figure 5. typical switching speed vs. pulse input current. i th ? input threshold current ? ma -40 2 t a ? temperature ? c 100 7 3 85 0 2 5 8 6 4 5 v dd = 5.0 v i ol = 20 a i ddh ? logic high output supply current ? ma -40 2.0 t a ? temperature ? c 100 5.5 hcpl-0708 fig 3 3.0 85 0 2 5 6.0 4.5 3.5 4.0 v dd = 5.0 v 2.5 5.0 i ddl ? logic low output supply current ? ma -40 4.0 t a ? temperature ? c 100 7.5 hcpl-0708 fig 4 5.0 85 0 2 5 8.0 6.5 5.5 6.0 v dd = 5.0 v 4.5 7.0 tp ? propagation delay ? ns 5 0 i f ? pulse input current ? ma 14 45 hcpl-0708 fig 5 10 11 7 9 50 30 20 25 5 40 6 8 10 12 13 15 35 v dd = 5.0 v t a = 25 c t phl t plh pw d v f ? forward voltage ? v 100 10 0.1 0.01 1.1 1.2 1.3 1.4 i f ? forward current ? ma 1.6 1.5 1.0 0.001 1000 i f v f + t = 25c a ?
10 application information bypassing and pc board layout the hcpl-0708 optocoupler is extremely easy to use. no external interface circuitry is required because the hcpl- 0708 uses high-speed cmos ic technology allowing cmos logic to be connected directly to the inputs and outputs. figure 6. recommended printed circuit board layout. figure 7. recommended printed circuit board layout. propagation delay, pulse-width distortion and propagation delay skew propagation delay is a fgure of merit which describes how quickly a logic signal propagates through a sys - tem. the propag a tion delay from low to high (t plh ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low figure 8. input t pl h t phl output i f v o 10% 90% 90% 10% v oh v ol 0 ma 50% 12 ma 2.5 v cmos 7 5 6 8 2 3 4 1 gnd c nc v dd v o i f xxx yw w c1, c2 = 0.01 f to 0.1 f v dd c2 xxx yww v o gnd i f c1, c2 = 0.01 f to 0.1 f as shown in figure 6, the only external component re - quired for proper operation is the bypass capacitor. ca - pacitor values should be between 0.01 f and 0.1 f. for each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. figure 7 illustrates the recommended printed circuit board layout for the hpcl-0708. to high. similarly, the propagation delay from high to low (t phl ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low. see figure 8.
figure 9. propagation delay skew waveform. figure 10. parallel data transmission example. propagation delay skew repr e sents the uncertainty of where an edge might be after being sent through an op - tocoupler. figure 10 shows that there will be uncertainty in both the data and clock lines. it is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. from these consider - ations, the absolute minimum pulse width that can be sent pulse-width distortion (pwd) is the diference between t phl and t plh and often determines the max i mum data rate capability of a transmission system. pwd can be expressed in percent by dividing the pwd (in ns) by the minimum pulse width (in ns) being tran s mitted. typical - ly, pwd on the order of 20 - 30% of the minimum pulse width is tolerable; the exact fgure depends on the par - ticular application. propagation delay skew, t psk , is an important parameter to co n sider in parallel data applications where synchro - nization of signals on parallel data lines is a concern. if the parallel data is being sent through a group of opto - couplers, diferences in propagation delays will cause the data to arrive at the outputs of the optocouplers at difer - ent times. if this diference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocouplers. 50% 50% t ps k i f v o i f v o 2.5 v, cmos 2.5 v, cmos data inputs clock data outputs clock t ps k t psk propagation delay skew is defned as the diference be - tween the minimum and maximum prop a gation delays, either t plh or t phl , for any given group of optocou plers which are operating under the same conditions (i.e., the same drive current, supply vol t age, output load, and op - erating temperature). as illustrated in figure 9 , if the in - puts of a group of optocouplers are switched either on or off at the same time, t psk is the diference between the shortest propagation delay, either t plh or t phl , and the longest propagation delay, either t plh or t phl . as mentioned earlier, t psk can determine the maximum parallel data transmission rate. figure 10 is the timing diagram of a typical parallel data application with both the clock and data lines being sent through the opto - couplers. the fgure shows data and clock signals at the inputs and outputs of the optocouplers. in this case the data is assumed to be clocked of of the rising edge of the clock. through optocouplers in a parallel application is twice t psk . a cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. the hcpl-0708 optocouplers ofer the advantage of guaranteed specifcations for propagation delays, pulse- width distortion, and propagation delay skew over the recommended temperature and power supply ranges.
1 for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies, limited in the united states and other countries. data subject to change. copyright ? 2007 avago technologies limited. all rights reserved. obsoletes av02-0877en av02-0877en january 8, 2008

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